VLSI STTP
Cadence Full Stack Training (Full Custom and Semi Custom)
The Department of Electronics Engineering (VLSI Design and Technology) organized Cadence Full stack training for both full and semi custom VLSI design flow from June 26 to June 28 2024. Faculty learnt both the flow with tools under cadence like NCSim, Innovus, Virtuoso, etc, in a full hands on training, which was conducted by Mr. Priyanshu from Entuple technologies. 
Xilinx Vivado and FPGA Design Training
Department of Electronics Engineering (VLSI Design & Technology) Organized Training on Xilinx Viado and FPGA Design Flow on 10/01/2025 from 10am to 5pm. Location : 304 Lab. Participants studied complete hands on tool of the Xilinx Vivado using two baords, the urbana and the PynQ SoC board which was essential for the academic semseters in the future.
“Spirituality in professionalism through Bhagwad Gita” and “NEP 2020: Implement IKS for Viksit Bharat 2047”
Department of Electronics Engineering (VLSI Design and Technology ) organized a Faculty Development Program on “Spirituality in professionalism through Bhagwad Gita” and “NEP 2020: Implement IKS for Viksit Bharat 2047” on Ist March 2025 . Our esteemed speaker of the session was Dr.VedVyas Dwivedi, Professor, Executive Vice President, Vedic teacher, Indus University, Gujarat. This session was a compelling intersection of ancient wisdom and modern educational policy. The core themes revolved around: Spirituality in Professionalism: Drawing insights from the Srimad Bhagavad Gita to instill ethical values and a sense of duty within professional conduct. NEP 2020 and IKS: Highlighting the National Education Policy 2020’s emphasis on integrating Indian Knowledge Systems (IKS) into contemporary education. Viksit Bharat 2047: Connecting these principles to the broader vision of a developed India by 2047, emphasizing how spiritual and traditional knowledge can contribute to national progress.
IESA Pune Chapter Meet, JW Mariott Pune
Prof. Nirmol Munvar attended the IESA Pune Chapter Meet at J. W. Mariott Pune on July 15 2024. Important things like how semiconductor will influence upcoming project naina, hardware security in vlsi and usage of vlsi for defence applications were discussed. Also light was shed on future project of semiconductor in maharashtra.
Visit to IESA Vision Summit 2024
HoD Ms. Nibha Desai visited the IESA vision summit 2024
IESA Vision Summit 2024 Propels India’s ESDM Sector with Focus on Design-Led Manufacturing” The India Electronics and Semiconductor Association (IESA) has wrapped up the 18th edition of its prestigious Vision Summit, held on January 24-25, 2024, at the Hilton in Bengaluru.
Members from Industry like NXP Semiconductors, D-matrix, ARM, Texas Instruments, Tata Elxsi, Cadence, Members from Academia like IIT-B, IISc – Bengaluru, BITS Pilani and Members of govt body from Govt of Tamil Nadu, Odisha, also were present, to talk about the future of semiconductor in the country.
Familiarization Session on Undergraduate VLSI Curriculum
16th May 2024,
Attended by: Ms. Aprajita Bera
For enhancing the quality of VLSI education staying updated with the latest developments in the field AICTE conducted a familarization workshop on model curriculum on May 16 2024 at AICTE HQ,New Delhi. This workshop was inaugurated by key note address by honorable chairman Prof.T G Sitharam. Distinguished professors from academia and emininet industry representatives from across the globe provided insights for curriculum delivery enabling significant contribution to the field of VLSI education and empower the nation in the semiconductor domain. Prof .Aprajita Bera attended this workshop from the department.
Dholera visit
HoD (Prof. Nibha Desai) of the Department of Electronics Engineering (VLSI Design and Technology) is thrilled to witness the Ground Breaking Ceremony of India’s first Semiconductor fabrication Lab by Shri Narendra Modi at Dholera on 13/03/2024.
