We are happy to announce that the Department of Electronics Engineering (VLSI Design and Technology) in collaboration with eInfochips and in association with IESA student chapter is organizing a two-week Summer Internship Program on “Modelling with Verilog HDL and Physical Design”. This internship offers a comprehensive hands-on learning experience focused on digital design and physical implementation. It’s an excellent opportunity to build core VLSI skills and work closely with industry experts.
Program Highlights:
Duration: 16th June to 28th June 2025 (2 Weeks)
Mode: Offline (SAKEC Campus)
Eligibility: B.Tech students interested in VLSI and hardware design.
Mentorship: Veteran Industry Trainers from eInfoChips with rich hands-on experience
Key Domains Covered:
- Verilog Modelling
- Physical Design
- Complete Hands-on Training with Real-time Simulations
- Industry-Relevant Project Work
Deliverables:
- Daily Live Sessions & Practical Labs
- One-on-one Mentorship
- Final Project Presentation & Certificate of Completion
Registration Link: click here
Registration Fees:
- 500 Rs non IESA Chapter Student
- 250 Rs IESA Chapter Student
Deadline to Apply:12/06/2025 Limited seats 30 Students only
Coordinators:
Mr. Nirmol Munvar – 8369153416
Ms. Heemalli Attarde – 8830059115
