VLSI Events

Department of Electronics Engineering (VLSI Design and Technology) in collaboration with eInfochips and in association with IESA student chapter is organized a two-week Summer Internship Program on “Modelling with Verilog HDL and Physical Design”. The internship offered a comprehensive hands-on learning experience focused on digital design and physical implementation. Student implemented Digital designs using Verilog and verified them with system verilog and further implemented them on physical layout hence completing the design flow of a digital system.

Duration: 16th June to 28th June 2025 (2 Weeks)

Week 1:

Basic Learning of Design and Verification and basic implementation of Verilog and System Verilog codes on Cadence Tools

Week 2:

Basic Design to real world digital systems and standard physical layout of system using Cadence Tools

Mode: Offline (SAKEC Campus)

Mentorship: Veteran Industry Trainers from eInfoChips with rich hands-on experience

Key Learning Outcomes :

1. Students are able to design verilog models pertaining to real world specifications
2. Students are able to verify said models using System verilog
3. Students are able to implement verified model in physical layouts

We are happy to announce that the Department of Electronics Engineering (VLSI Design and Technology) in collaboration with eInfochips and in association with IESA student chapter is organizing a two-week Summer Internship Program on “Modelling with Verilog HDL and Physical Design”. This internship offers a comprehensive hands-on learning experience focused on digital design and physical implementation. It’s an excellent opportunity to build core VLSI skills and work closely with industry experts.

Program Highlights:

Duration: 16th June to 28th June 2025 (2 Weeks)
Mode: Offline (SAKEC Campus)

Eligibility: B.Tech students interested in VLSI and hardware design.

Mentorship: Veteran Industry Trainers from eInfoChips with rich hands-on experience

Key Domains Covered:

1. Verilog Modelling
2. Physical Design
3. Complete Hands-on Training with Real-time Simulations
4. Industry-Relevant Project Work

Deliverables:

1. Daily Live Sessions & Practical Labs
2. One-on-one Mentorship
3. Final Project Presentation & Certificate of Completion

Registration Link: click here

Registration Fees:

• 500 Rs non IESA Chapter Student
• 250 Rs IESA Chapter Student

Deadline to Apply:12/06/2025 Limited seats 30 Students only

Coordinators:
Mr. Nirmol Munvar – 8369153416
Ms. Heemalli Attarde – 8830059115

The Parent-Teacher Meeting (PTM) conducted on 15th March 2025 of the Electronics Engineering (VLSI Design and Technology) department, in CR-74 between 10.30 AM-12.30PM was a constructive event aimed to discuss students’ academic progress, provide updates on upcoming activities, and address individual concerns. The session, led by Prof. Nibha Desai, was well-organized and attended by a large number of parents and guardians. The meeting followed a structured agenda, covering the following key points:

1. Attendance:
   Discussion centered on student attendance in theory and practical sessions. Parents were encouraged to ensure consistent attendance to enhance their ward’s academic performance.
2. Results:
   Semester III results were analyzed, with insights shared on overall performance and areas needing improvement. Individual progress was discussed during one-on-one interactions.
3. Supplementary Exam Preparation:
   Prof. Nibha Desai provided guidance for students appearing in upcoming supplementary exams, emphasizing effective study strategies.
4. Upcoming Exams:
   Details of the Continuous Comprehensive Evaluation (CCE), Continuous Internal Assessment Practical (CIAP), End Semester Practical (ESEP), and End Semester Examination (ESE) were shared, along with tips for preparation and timelines.
5. Projects:
   Students were encouraged to participate in innovative projects.
6. Appreciation:
   Students who excelled in technical and non-technical activities were recognized and appreciated for their dedication and achievements.
7. Opportunities in Semiconductors:
   Prof. Nibha Desai shared insights from the recent IESA Summit, highlighting career opportunities in the semiconductor industry and encouraging students to explore this rapidly growing field.
8. One-to-One Interaction with HOD:
   Parents were given the opportunity to interact directly with the Head of Department to discuss academic and personal concerns related to their ward. The meeting was highly interactive and constructive. The PTM concluded with a collective commitment from parents and faculty to work together for the holistic development of students.                                                                                                                                                                                    

From 1st to 4th January 2025, The Department of Electronics Engineering (VLSI Design and Technology) conducted a python app development internship for students. The Students learnt the basics of python right from the app development side and learning both front end and back end and integrating them to make a fully functional application. The session(s) were delivered by Prof. Nirmol Munvar (Assistant Professor) from VLSI design and Technology with Prof. Mridul Saxena as Co-Coordinator for the event

The valedictory of the same was held at 18th January 2025, for which students presented projects made after learning from the internships.

Department of Electronics Engineering (VLSI Design and Technology) in association with Indian Society of VLSI Education conducted an outreach program on “Chip Designing and Cyber Security” on 30th August 2024.This outreach program was aimed to inspire the young minds for exploring the semiconductor domain and making the audience aware about the plethora of opportunities for Innovation and development in Electronics and semiconductor domain . This outreach program focuses on the different aspects of chip designing and the attributes required for a candidate to excel in this domain and the impact of cyber security in chip designing. Dr. D. K. Yadav Professor, Department of Computer Science & Engineering National Institute of Technology, Jamshedpur President, Indian Society for VLSI Education Ranchi gave the keynote lecture on Cyber Security and its impact on Chip Designing. Dr Vijay Nath,Associate Professor, VLSI Design Group, Department of Electronics & Communication Engineering,,Birla Institute of Technology Mesra Ranchi General Chair, Indian Society for VLSI Education Ranchi gave an expert talk on Chip Designing and also gave insights on the Semiconductor mission and the expected contribution of youngsters for making the dream of Vikshit Bharat a reality by 2047. All the queries of the participants were addressed in the interactive session.We are thankful to SAKEC Management, Principal Sir Dr. Bhavesh Patel and ISVE for inaugurating Zonal Centre of ISVE in Mumbai region.

20th July 2024 witnessed the confluence of parents and teachers of the Electronics Engineering (VLSI Design and Technology) department, for the Parent-Teacher meeting at the 4th floor seminar hall between 10:00 AM to 1:00 PM. HoD, Prof Nibha Desai, and the faculty of the department briefed the parents and students on the things to come in the near future pertaining to the rules of attendance, discipline and overall student conduct, curriculum exam scheme under autonomy, teaching-learning processes, methods adopted, and various other aspects of the engineering course along with the respective additional Co-curricular and Extra-curricular activities to be conducted in the due course of time. Finally, the Event concluded with a visit to the 210 VLSI lab, where parents could see for themselves, and be assured about the Lab infrastructure and facilities available to foster the efficient teaching-learning process for the rigorous course of engineering.

The Awareness session on VLSI Design and Technology was conducted by the Department of Electronics Engineering (VLSI Design and Technology) in Vidya Prasarak Mandal Polytechnic (VPM) college, Thane on 16th April 2024. The session aimed to provide the students with awareness about VLSI Design and job opportunities in the VLSI domain. Prof. Reshma Patil brief about the concepts of VLSI design flow. Prof. Ashwini Jagtap explained about job Opportunities and recent projects announced by the government in VLSI Domain. The student’s response was amazing for the session and they were excited to hear about new domains and opportunities in the future.

Date: 29th February 2024 – 3rd March 2024

Location: Ahmedabad

Faculty Coordinator: Professor Nirmol Munvar

Faculty Members: Prof. Amit Tiwari, Prof. Reshma Patil, Prof. Ashwini Jagtap

Overview: The industrial visit conducted by Shah and Anchor Kutchhi Engineering College was a collaborative effort between the Department of Electronics and Computer Science and the Department of Electronics Engineering (VLSI Design and Technology). The visit aimed to provide students with practical exposure to industries relevant to their field of study. The visit spanned from 29th February to 3rd March 2024, with visits to prominent companies in Ahmedabad.

Industrial Visits:

1. EInfochips, An Arrow Company Ahmedabad: Date: 1st March 2024 Industry Focus: Semiconductor IC and Chip Design Representatives: Mr. Bhavin Kakani and Mr. Dipesh Panchal

The visit to EInfochips, a leading company specializing in semiconductor IC and chip design, provided students with valuable insights into the latest trends and technologies in VLSI. Mr. Bhavin Kakani and Mr. Dipesh Panchal delivered an informative session, focusing on chip and IC design, as well as emerging trends in VLSI. Their expertise and practical examples helped students grasp complex concepts and understand real-world applications.

2. GVK Healthcare Services: Date: 2nd March 2024 Industry Focus: Real-time Medical Emergencies and Server Telecommunication

The visit to GVK Healthcare Services offered students exposure to real-time medical emergency management and server telecommunication systems. Through interactive sessions and demonstrations, students gained insights into the integration of technology in healthcare and telecommunications sectors. The visit facilitated a deeper understanding of how electronics and computer science principles are applied in critical industries.

Learning Experience: The industrial visit provided students with a unique opportunity to bridge the gap between theoretical knowledge and practical applications. By witnessing first-hand the operations and technologies used in industry settings, students gained a deeper understanding of their field of study. The sessions conducted by industry experts were particularly beneficial, offering valuable insights and igniting students’ curiosity about emerging technologies and trends.

Faculty Involvement: Under the guidance of Professor Nirmol Munvar and Professor Amit Tiwari and the support of faculty members including Prof. Reshma Patil, and Prof. Ashwini Jagtap, the industrial visit was meticulously organized and executed. Faculty members played a crucial role in facilitating interactions between students and industry representatives, ensuring a productive and enriching learning experience for all participants.

Conclusion: The collaborative industrial visit by Shah and Anchor Kutchhi Engineering College served as a platform for students to explore the practical applications of their academic knowledge. By engaging with industry professionals and experiencing firsthand the latest technologies and trends, students gained invaluable insights that will undoubtedly enhance their academic and professional journey. The success of the visit underscores the importance of such initiatives in nurturing well-rounded and industry-ready engineers.