Department of Electronics Engineering (VLSI Design and Technology) in collaboration with eInfochips and in association with IESA student chapter is organized a two-week Summer Internship Program on “Modelling with Verilog HDL and Physical Design”. The internship offered a comprehensive hands-on learning experience focused on digital design and physical implementation. Student implemented Digital designs using Verilog and verified them with system verilog and further implemented them on physical layout hence completing the design flow of a digital system.
Duration: 16th June to 28th June 2025 (2 Weeks)
Week 1:
Basic Learning of Design and Verification and basic implementation of Verilog and System Verilog codes on Cadence Tools
Week 2:
Basic Design to real world digital systems and standard physical layout of system using Cadence Tools
Mode: Offline (SAKEC Campus)
Mentorship: Veteran Industry Trainers from eInfoChips with rich hands-on experience
Key Learning Outcomes :
- Students are able to design verilog models pertaining to real world specifications
- Students are able to verify said models using System verilog
- Students are able to implement verified model in physical layouts
