Shah and Anchor Kutchhi Engineering College in association with IETE Mumbai and IIC 5.0 organized winter Internship on VLSI Design from 26th December 2022 to 6th January 2023. The internship was organized with an aim to make the students industry ready in the field of VLSI Design. In the first part of the internship, lecture and practical sessions were conducted by Dr. Sushma Srivastava and Prof. Shridhar Sahu for 5 days starting from 26th December 2022. The lecture sessions included MOSFET physics, MOSFET operation, CMOS inverter design, CS amplifier design. The designed circuits were implemented and simulated in the industry standard CADENCE toolset’s Virtuoso tool. They were taught to design schematic as well as layout of the circuit and perform different types of simulations as required. They were also taught to generate the GDS-II stream file which is given for fabrication.
The students were then assigned a problem statement on the design and implementation of a current source load CS amplifier based on the knowledge acquired during the lecture and practical sessions held earlier. They completed this project in the remaining period of the internship and a competition was conducted based upon the design and specifications achieved.. They were supposed to design the circuit for the required specifications on paper and then implement and simulate the circuit on the Virtuoso tool. After successfully designing and implementing the schematic of the circuit, the students had to design the layout of the circuit and perform the post layout simulations for the same parameters and were expected to achieve minimum change as compared to schematic simulations.
The students were divided into six groups and performed overwhelmingly well and all groups achieved the required specifications by designing and implementing the circuit designed on the virtuoso tool. Rubrics were disseminated to the participants at the start of the competition and the groups were graded accordingly. Viva-voce was part of the rubrics and was conducted by Mr. Abhishek Kadam, IITB Research Scholar. Top two performers were awarded winner certificates and prize money. Mr. Abhishek Kadam delivered a session on VLSI Chip Design Flow & Neuromorphic Engineering on the last day of the internship and after that, valedictory function was conducted which was graced by the presence of Dr. Bhavesh Patel, Principal SAKEC, Mr. Abhishek Kadam, Dr. Vinutha T. P., ISF SAKEC Coordinator, Dr. Sushma Srivastava, Prof. Shridhar Sahu and students. Dr. Bhavesh Patel talked about the increasing demand in the field of VLSI Design and the relevance of this internship. All students were presented with the participation certificates by Mr. Abhishek Kadam
