VLSI Announcements
ESEP Time Table Sem IV Sem VI MTech Sem II
Backlog ESEP, CIAP CCE SEM II SEMIV Time Table
MSE Time Table FH 2026 SY TY HN PG
TY / SY CCE CIAP ESEP SLA Supplementary Time Table
ESEP Time Table PG 2025 SEM I
Silicon Summit 2025 – Academia–Industry Conclave
Greetings from Shah And Anchor Kutchhi Engineering College!
We are delighted to share that our Department of Electronics Engineering (VLSI Design & Technology) is organizing “Silicon Summit – An Academia-Industry Conclave on 13th November 2025 at SAKEC.
We invite you as a participant for our conclave in a Panel Discussion on Semiconductor Opportunities and Innovation. The Panel will have eminent speakers from Industry and academia and Panel Discussion will be conducted for the tracks : Curriculum Development Workshop , Training & Workshops, Research &Internship and Placement.
We are delighted to share that our Department of Electronics Engineering (VLSI Design & Technology) is organizing “Silicon Summit – An Academia-Industry Conclave on 13th November 2025 at SAKEC.
We invite you as a participant for our conclave in a Panel Discussion on Semiconductor Opportunities and Innovation. The Panel will have eminent speakers from Industry and academia and Panel Discussion will be conducted for the tracks : Curriculum Development Workshop , Training & Workshops, Research &Internship and Placement.
Please register with the link given
For further queries please connect with:
Ms. Aprajita Bera: 9833748985
Mr.Nirmol Munvar : 8369153416
UG SEM I MSE Time Table Odd 25-26
M.Tech SEM I MSE Time Table Odd 25-26
ESEP Odd Sem 2025-26 Sem III and V
One-week Faculty Development Programme approved by AICTE under the Training and Learning (ATAL) Academy scheme
We are delighted to share that our proposal for a one-week Faculty Development Programme has been approved by AICTE under the Training and Learning (ATAL) Academy scheme.
The FDP, titled “Periodic Innovation in the Perspective of VLSI of Semiconductor ICs,” will be held from 15th to 20th December 2025.
This programme is proudly organised by the Department of Electronics Engineering (VLSI Design & Technology) in collaboration with the Department of Electronics & Telecommunication Engineering.
Session on “How to ask Questions”
Department of Electronics Engineering(VLSI Design and Technology) is organizing a session on “How to ask Questions” on 10th July 2025 , from 2 pm to 4 pm. This session is aimed at improving participants’ critical thinking, communication, and inquiry skills, and can be integrated into courses focused on soft skills, problem-solving, or active learning environments. Looking forward to see you all in the session. Please find the details below:
Venue : 7th Floor Auditorium
Date : 10th July 2025, 2:30 pm to 4 pm
Speaker : Mr. Milind Kamble : Head of Delivery and Operations, TCS Mumbai
Registration form : link
Please connect with the undersigned for further queries
Aprajita Bera
9833748985
CHIP NEXUS – Your Gateway to the Future of VLSI (Student Development Program)
Join Us for CHIP NEXUS – Your Gateway to the Future of VLSI!
Department of Electronics Engineering (VLSI Design and Technology)
Student Development Program
IESA Student Chapter in Collaboration with SAKEC IIC 7.0
Curious about the future of VLSI and semiconductor technology? Want to explore exciting career opportunities in this rapidly evolving industry? CHIP NEXUS is your chance to gain exclusive insights from industry experts!
What to Expect?
Cutting-edge VLSI trends & innovations shaping the semiconductor landscape
Explore career paths & job opportunities in the semiconductor industry
Discover emerging technologies transforming chip design & fabrication
Date: 5th April 2025
Venue: 4th Floor Seminar Hall
Time: 10 am to 12 pm
Don’t miss out on this power-packed session filled with knowledge, networking, and opportunities!
Register Now & Secure Your Spot!: https://docs.google.com/forms/d/e/1FAIpQLSehDWtfDkH1GLkIM2kbYzKxDhG_boqssqWTFdbMtDxFyZjc2g/viewform
Contact us:
Shreeya Mhatre: +91 9769918236
Chinmay Vanage: +91 91671 83071
Prof. Mridul Saxena: +91 87459 53523
Session on “Spirituality in professionalism through Bhagwad Gita” and “NEP 2020: Implement IKS for Vikshit Bharat 2047”
Department of Electronics Engineering (VLSI Design and Technology ) is organizing Session on “Spirituality in professionalism through Bhagwad Gita” and “NEP 2020: Implement IKS for Vikshit Bharat 2047” on Ist March 2025 . Our esteemed speaker of the session is Dr.VedVyas Dwivedi, Professor, Executive Vice President, Indus University, Gujarat. You are cordially invited to attend this session and explore the hidden treasures of our rich heritage. The details of the session are as follows.
Date : 1st March 2025
Time : 10 am onwards
Venue : 7th Floor Auditorium
Please register in the given link : Registration Link
Please feel free to connect with the undersigned for further details.
Prof.Mridul Saxena : 8745953523
Prof.Aprajita Bera : 9833748985
App Development Internship Using Python
Department of Electronics Engineering (VLSI Design and Technology) brings you App development Internship in Python. It is no secret that python is now the go to language for almost every domain in engineering, From Data Science to Processor Design, From Image Processing to Design Automation. So grab your chance now to undergo the Application Development Internship with Python.
Features are:
- Completely Hands on
- Beginner Friendly
- Open for all
- Real world Applications
- Developer Tips and Tricks
- Using State of Art Professional Tools
This internship is free for Students of Shah and Anchor Kutchhi Engineering College and for students outside SAKEC, the cost is merely 500 Rs. So hurry up as there are only limited seats.
For any Queries please contact:
Co-Ordinator and Speaker:
Prof. Nirmol Munvar – 8369153416
Co-Co-Ordinator:
Prof. Mridul Saxena – 8745953523
Advancement in Sustainable Semiconductor ICs: An Expert Lecture Series
Expert Lecture series on “Advancement on sustainable Semiconductor ICs” will be organized by the Department of Electronics Engineering (VLSI Design and Technology) from 9th December to 13th December 2024 . The series will be held on MS Teams on the following dates. All the faculty members are invited to join the lecture series and make this event a huge success.
The schedule is as follows:
December 9 2024 : Mr.Sudhir Naik, IESA Head, Mid West region, Cofounder e-Infochips Pvt Ltd
6: 00 pm: 6:30 pm Talk 0n ” SDG 7 Goal for energy and role of Semiconductor”.
December 11 2024 : Dr. Mayur Chhipa, ISBAT University California, Kampala
7:30 pm : 9:00 pm : Talk on “Photonics Integrated Circuit “.
December 13 2024: Dr. Naznin Akter, Ph.D., PMP®️, LSSGB
7:30 pm : 9:00 pm : Talk on ” Research and development in the Semiconductor industry including Sustainability, and the CHIPS Act. “.
Link to Register :Registration form
Please connect with the undersigned for any queries.
Aprajita Bera
9833748985
One Day Outreach Program on Chip Designing and Cyber Security by ISVE (Indian Society for VLSI Education)
Department of Electronics Engineering (VLSI Design and Technology) in association with Indian Society of VLSI education is conducting an outreach program on “Chip Designing and Cyber Security” on 30th August 2024.This outreach program is aimed to inspire the young minds for exploring the semiconductor domain and making the audience aware about the plethora of opportunities for Innovation and development in Electronics and semiconductor domain . This outreach program focuses on the different aspects of chip designing and the attributes required for a candidate to excel in this domain and the impact of cyber security in chip designing.
Esteemed speakers
Dr Vijay Nath,Associate Professor, VLSI Design Group, Department of Electronics & Communication Engineering,,Birla Institute of Technology Mesra Ranchi
General Chair, Indian Society for VLSI Education Ranchi
Topic: Chip DesigningDr. D. K. Yadav
Professor, Department of Computer Science & Engineering National Institute of Technology, Jamshedpur
President, Indian Society for VLSI Education Ranchi
Topic : Cyber Security
General Chair, Indian Society for VLSI Education Ranchi
Topic: Chip DesigningDr. D. K. Yadav
Professor, Department of Computer Science & Engineering National Institute of Technology, Jamshedpur
President, Indian Society for VLSI Education Ranchi
Topic : Cyber Security
Convenor: Prof.Nibha Desai
Co-ordinator : Prof. Aprajita Bera
Date and time: 30th August 2024, 10 :00 am onwards
Venue : 4th Floor, Seminar Hall
Parent Teacher Meeting July 20 2024
Dear Parents,
Shah and Anchor Kutchhi Engineering College, Electronics Engineering (VLSI Design and Technology) Department cordially invites you to the Parent-Teacher meeting scheduled on 20 July 2024, at 4 Floor Seminar Hall from 10:30 am onwards.
We look forward to meeting you in person to discuss our mutual goal of your child’s success path ahead.
Parent_teacher Meeting
Date: 20 July 2024,
Time: 10:30 am to 1 pm,
Venue: 4 Floor Seminar Hall
Touching Lives: Fabricating your dream career in semiconductor
Touching Lives: Fabricating your dream career in semiconductor
About Event
“The dream of India becoming a semiconductor hub for the world is not a distant fantasy but an attainable reality. We have the talent, the resources, and the ambition to become the fore-bearers of global technology innovation. We are looking forward for your active participation to rejoice India’s semiconductor renaissance in the Student Development Program organized by Department of Electronics Engineering (VLSI Design and Technology) on 6th July 2024 on “Touching Lives : Fabricating your dream career in semiconductors” . Lets hear from our esteemed dignitaries and explore the much needed skills and competencies expanding to all avenues of semiconductor design and technologies. Together lets embark on our path to make India as semiconductor superpower.”
Esteemed Speakers:
Mr.Sudhir Naik,
IESA treasurer, co-founder eInfochips, An Arrow Company
Mr.Milind Kamble,
Delivery Centre Head,TCS Mumbai
Date and time:
6th July 2024, 10 :00 am onwards
Venue :
7th Floor Auditorium
Registration Link:
Coordinator:
Mrs. Aprajita Bera – 9833748985
Convener:
Mrs. Nibha Desai
